1/8 november 2000 AN404 application note write protection in the i 2 c and xi 2 c eeprom families eeprom is one of the most flexible of the non-volatile memory technologies, capable of being read, erased and written a byte at a time, or a block at a time. although this flexibility is of obvious advantage, it is desirable that it be tempered with some degree of protection against inadvertent write or erase (caused by noise, software crash, hardware failure, or some other malfunction). after all, the main reason for choosing to use non-volatile memory is to be able to store persistent data: data that is important enough to be remembered through periods of power failure, and from one power-on session to the next. the m24cxx and st24/25xxx families of serial eeprom devices are fully compatible with the i 2 c proto- col. in addition, though, each device offers extra data protection facilities for use in guarding against the possibility of inadvertent write operations. global protection against inadvertent erase/write the write control (wc ) input is present on the m24cxx and st24/25wxx devices (not on st24/25cxx devices). it offers a mechanism for the global protection of the memory contents, for example as shown in figure 1. when wc is driven high by the external circuitry (normally by the bus master), write and erase operations are ignored; when driven low, they are accepted, and executed. figure 1. eeprom interface using the write control line a typical application normally holds the wc line high, to put the eeprom in its protected (read-only) mode. then, when a write or erase operation is to be performed, it performs the following sequence: 1. the wc line is taken low 2. the write or erase operation is performed. 3. the wc line is taken high again. any write or erase operations received whilst the eeprom is in its protected mode are ignored. the par- ticular behaviour of the page write operation, though, warrants some further attention: when the eeprom is in its unprotected mode (wc held low), and a page write operation is issued, the devices internal address counter is incremented after each received byte. when the last byte is received, this leaves the internal address counter at the right value for the first byte of the following page write operation. when the eeprom is in its protected mode (wc held high), and a page write operation is issued, no data are written, but the internal address counter is still incremented after each byte, except for the last received byte C the eeprom internal address counter remains at the last received byte address. ai01108b write control bus master scl sda st24xxx st25xxx eeprom
AN404 - application note 2/8 selective protection against inadvertent write the members of the st24/25x04, st24/25x08 and st24/25x16 families each offer a selective protection mechanism, in addition to the global protection offered by the wc pin. if the pre pin is held high, and the bit b2 in the last byte of the eeprom contains a 0, part of eeprom becomes write protected, and be- haves like rom. the remaining area continues to function as unprotected eeprom (though this can still be protected by taking the wc input high). the protected region extends from the last byte of the eeprom down to the address pointed to by the most significant bits in the last byte (as shown in figure 2). the last byte in the memory has an address of 1ffh in the st24/25x04, of 3ffh in the st24/25x08, and of 7ffh in the st24/25x16. the maximum size of the protected memory, as depicted in figure 2, is: n 256 bytes (the top half of the memory) for the st24/25c04 and st24/25w04 n 256 bytes (the top quarter of the memory) for the st24/25c08 and st24/25w08 n 1024 bytes (the top half of the memory) for the st24/25c16 and st24/25w16. figure 2. size and location of the protected areas under the control of the pre signal ai01110b address pointer 1ffh max protected area 100h 000h st2xw04 st2xc04 address pointer 7ffh max protected area 400h 000h st2xw16 st2xc16 address pointer 3ffh max protected area 300h 000h st2xw08 st2xc08
3/8 AN404 - application note using the pre pin to control the writing of the protected area the sequence for protecting an area of the memory is as follows: 1. the pre pin is held low (by the bus master). 2. the new contents of the memory are written. 3. the address of the start of the protected region is written to the last byte. the contents of bit b2 are set to 0. (see the next page for the precise format of this byte). 4. pre pin is taken high (by the bus master). data above the byte pointed by the address pointer are now write protected, and cannot be modified. this part of the eeprom is now functionally equivalent to a block of rom. the dynamic use of the pre signal, for controlled writing of the protected region by the bus master, is similar to that for the wc signal. that is, the sequence is as follows: 1. the pre line is taken low 2. the write operation is performed. 3. the pre line is taken high again. the pre pin may be driven dynamically by the bus master, as indicated in the above sequence. alterna- tively, it can be wired permanently to v cc (to disable further writes once the manufacturer has pro- grammed the protected area) or wired permanently to v ss (if the pre control is not to be used at all). figure 3. static drive of the pre signal alternatively, the pre pin can be pulled high, as shown in figure 3. this arrangement allows the applica- tion manufacturer to program the protected area of the eeprom as follows: 1. the components, including the eeprom and its pull-up resistor, are assembled on the board. 2. the pre pin is forced low (typically using a short circuit between the pre pin and the v ss pin). 3. the application data (such as fabrication date, serial number, customer or dealer area) are written in the protected area, along with the address pointer to the start of the application data, and the value 0 in bit b2 (see the next page for the format of this address). 4. the external short circuit of the pre line is removed. ai01111 sda v cc st24wxx st24cxx scl v ss pre i 2 c bus 1k w external short circuit
AN404 - application note 4/8 when the application board is delivered to the end user, the data in the application area cannot be modi- fied. it is as if they were written in rom. the remainder of the memory can be used, by the end user, as normal eeprom. format of the last byte the last byte of the eeprom contains two fields of data: n the write control bits (in the least significant portion) n the address of the start of the protected area (in the most significant portion) bit b2 of the write control bits is used, in combination with the input on the pre pin, to control the write access to the protected area. that is, the write protection function can be controlled by hardware, via the pre input, or by software, via the setting of the b2 bit. the control function is as follows: n the area of memory is write protected if pre is held high and bit b2 of the last byte is set to 0. n the area of memory is write enabled if pre is held low or bit b2 of the last byte is set to 1. the address of the start of the protected area only represents the most significant portion of the physical address. that is, the address of the start of the protected area can only be specified in steps of 8 for the st24/25w04 and st24/25w08, and in steps of 16 for the st24/25w16. figure 4 shows the format for the last byte for members of the st24/25x04 and st24/25x08 families. n the 5 most significant bits (b7 to b3) make up the address field n the 3 least significant bits (b2 to b0) make up the write control field the address pointer is treated as an 8-bit integer with the 5 most significant bits derived from the address field, and the 3 least significant bits of the address assumed to be 0 (independent of the setting of the b2, b1 and b0 control bits). the address pointer can therefore define a protected area with a maximum size of 256 bytes, in steps of 8 bytes. figure 4. format of the last byte and the address pointer in 4k and 8k devices ai01112 top byte maximum size = 256 bytes protected area 000h st2xw04, st2xw08 st2xc04, st2xc08 b7 b6 b5 b4 b3 0 0 0
5/8 AN404 - application note figure 5 shows the format for the last byte for members of the st24/25x16 family. n the 4 least significant bits (b3 to b0) make up the write control field n the 4 most significant bits (b7 to b4) make up the address field the address pointer is treated as a 10-bit integer with the 2 most significant bits derived from the state of the pb1 and pb0 pins of the chip, the next 4 bits derived from the address field, and the 4 least significant bits of the address assumed to be 0. the address pointer can therefore define a protected area with a maximum size of 1024 bytes, in blocks of 256 bytes (as specified externally by the state of the pb1 and pb0 pins), and in steps of 16 bytes (because the 4 least significant bits are taken to be 0). figure 5. format of the last byte and the address pointer in 16 k device use of the device select byte and chip enable pins many of sts i 2 c devices (notably the members of the st24/25x01, st24/25x02 and m24cxx families) have data dependent chip enable pins (e0, e1 and e2). these inputs are designed principally to allow more than one device to be placed on the i 2 c bus, as described in application note an1005 . a unique three-bit address, or identification code, is hard-wired to each chips pins, and each chip only responds to commands on the i 2 c bus that bear the corresponding device select code in the device select byte. however, if the i 2 c bus is not fully populated, it is possible to use this facility as an extra protection mech- anism. if the application hardware detects an abnormal condition, such as excessive noise on the bus or power supply levels going out of specification, it can set the e0, e1 and e2 inputs to the identifier of a non- existent device. provided that the microcontroller never addresses this non-existent device, the eeprom will be hidden from any further accesses (read accesses will be prevented, too, as well as erase and write accesses). ai01113 7ffh maximum size = 1024 bytes protected area 000h st2xw16 st2xc16 b7b6b5b40000 block number (pb0, pb1)
AN404 - application note 6/8 pin-out and device select byte: variations within the family three mechanisms for write protection have been described in this document. only the members of the st24/25x04 and st24/25x08 families offer all three mechanisms. usually, the designer is restricted to the one or two mechanisms offered by the device that is being used in the application. it is, of course, probably memory capacity, not write protection mechanism, that determines the choice of eeprom for the appli- cation. so, the designer needs to consult the data sheet of the chosen device when deciding on an appro- priate write protection strategy. table 1 summarises the differences in pin-out for each of the members of the st24/25xxx family. for il- lustration, figure 6 shows the pin-out of the st24/25c01, serial eeprom, 1 kbit device. figure 6. pin-out for the st24/25c01 serial eeprom (1 kbit) the pin-out varies, for pins 1, 2, 3 and 7, between the individual members of the st24/25cxx and st24/ 25wxx families, as summarised in table 1. table 1. pin compatibility in the st24/25xxx series pin number12345678 st24c01/st25c01 e0 e1 e2 v ss sda scl mode v cc st24w01/st25w01 e0 e1 e2 v ss sda scl wc v cc st24c02/st25c02 e0 e1 e2 v ss sda scl mode v cc st24w02/st25w02 e0 e1 e2 v ss sda scl wc v cc st24c04/st25c04 pre e1 e2 v ss sda scl mode v cc st24w04/st25w04 pre e1 e2 v ss sda scl wc v cc st24c08/st25c08 pre nc e v ss sda scl mode v cc st24w08/st25w08 pre nc e v ss sda scl wc v cc st24c16/st25c16 pre pb0 pb1 v ss sda scl mode v cc st24w16/st25w16 pre pb0 pb1 v ss sda scl wc v cc st24e16/st25e16 e0 e1 e2 v ss sda scl wc v cc sda v ss scl mode e1 e0 v cc e2 ai02407 st24c01 st25c01 1 2 3 4 8 7 6 5
7/8 AN404 - application note the variation in the use of pins 1, 2 and 3 leads to variations in the composition of the first byte of each i 2 c data transfer (the device select byte), as summarised in table 2. table 2. composition of the device select byte bits in the device select byte b7 b6 b5 b4 b3 b2 b1 b0 st24c01/st25c01 1 0 1 0 e2 e1 e0 r/w st24w01/st25w01 st24c02/st25c02 1 0 1 0 e2 e1 e0 r/w st24w02/st25w02 st24c04/st25c04 1 0 1 0 e2 e1 a8 r/w st24w04/st25w04 st24c08/st25c08 1 0 1 0 e a9 a8 r/w st24w08/st25w08 st24c16/st25c16 1 0 1 0 a10 a9 a8 r/w st24w16/st25w16 st24e16/st25e16 1 0 1 0 e2 e1 e0 r/w
AN404 - application note 8/8 if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail addresses: apps.eeprom@st.com (for application support) ask.memory@st.com (for general enquiries) please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 2000 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - finland - france - germany - hong kong - india - italy - japan - malaysia - malta - morocco - sing apore - spain - sweden - switzerland - united kingdom - u.s.a. http://www.st.com
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